1. Field of the Invention
The present invention relates to a method for driving a plasma display panel (PDP), which is suitable for driving a surface discharge AC type PDP. This surface discharge type has a pair of display electrodes arranged in parallel on a front substrate or a back substrate. The display electrodes become an anode and a cathode in display discharge for securing luminance. One of tasks to be solved for an AC type plasma display panel is light emission in an area that is not to be lighted in a screen, i.e., background light emission.
2. Description of the Prior Art
FIG. 1 shows a cell structure of a typical surface discharge type plasma display panel. A PDP 1 includes a pair of body structures (having a substrate and cell elements arranged on the substrate). A front substrate body structure includes a glass substrate 11, and display electrodes X (first display electrodes) and display electrodes Y (second display electrodes) are arranged on the inner surface of the glass substrate 11 so that a pair of display electrode X and display electrode Y corresponds to one row of the matrix display. Each of the display electrodes X and Y includes a transparent conductive film 41 that forms a surface discharge gap and a metal film 42 that is overlaid on the end rim portion of the transparent conductive film 41, which are covered with a dielectric layer 17 made of a low melting point glass and a protection film 18 made of magnesia. A back substrate body structure includes a glass substrate 21, and address electrodes A are arranged on the inner surface of the glass substrate 21 so that one address electrode A corresponds to one column. Each of the address electrodes A is covered with a dielectric layer 24, on which partitions 29 are disposed for dividing a discharge space into plural spaces corresponding to columns. A surface of the dielectric layer 24 and side faces of the partitions 29 are covered with fluorescent material layers 28R, 28G and 28B for a color display. Italic letters (R, G and B) in FIG. 1 denote light emission colors of the fluorescent materials. The colors are arranged in a repeating pattern of R, G and B in which cells of the same column have the same color. The fluorescent material layers 28R, 28G and 28B are excited locally by ultraviolet rays that are emitted by a discharge gas so as to emit light. A structure at an intersection point of a row and a column is a cell, and three cells constitute one pixel of a display image. Since the cell is a binary light emission element, it is required to control integral light emission quantity of each cell for each frame in order to display a color image.
FIG. 2 shows an example of frame division for a color display. The color display is one type of gradation display, and a display color is determined by a combination of three luminance values of red, green and blue colors. The gradation display is realized by a method in which one frame is made up of plural subframes that have weights of luminance values. In FIG. 2, one frame is made up of eight subframes (each subframe is abbreviated as SF in FIG. 2 and following explanation). When a ratio of the integral light emission quantity of these SFs, i.e., a ratio of weights of luminance values is set equal to or nearly equal to 1:2:4:8:16:32:64:128, 28 (=256) gradation levels can be reproduced. For example, in order to reproduce a gradation level 10, cells are lighted in SF2 of weight 2 and SF4 of weight 8 while cells are not lighted in the other SFs.
An initialization period, an address period and a sustaining period are assigned to each SF. An initialization process is performed during an initialization period for equalizing wall voltages in all cells, and addressing process is performed during an address period for controlling the wall voltage of each cell in accordance with display data. Then, a sustaining process is performed during a sustaining period for generating display discharge only in cells to be lighted. One frame is displayed by repeating the initialization process, the addressing process and the sustaining process. However, contents of the addressing are usually different for each subframe. In addition, a length of the sustaining period is not fixed but changes corresponding to the weight of luminance.
FIG. 3 shows conventional driving waveforms. FIG. 3 shows generally the waveforms for the address electrode A and the display electrode X. Furthermore, FIG. 3 shows waveforms for the display electrode Y(1) of the first line and the display electrode Y(n) of the last line as representatives.
A positive blunt wave is applied to the display electrode Y during the initialization period. Namely, a bias control is performed so as to increase a potential of the display electrode Y simply. In order to accelerate reaching a predetermined potential, a positive offset bias is applied to the display electrode Y while a negative offset bias is applied to the display electrode X. After that, a negative blunt wave is applied to the display electrode Y. Namely, a bias control is performed in which a potential of the display electrode Y is decreased simply. A potential of the address electrode A is maintained at the ground level (0 volt) during the entire initialization period. A scan pulse is applied to each display electrode Y one by one during the address period. Namely, a row selection is performed. In synchronization with the row selection, an address pulse is applied to the address electrode A that corresponds to the cell to be lighted in the selected row. Address discharge is generated in the cell to be lighted that is selected by the display electrode Y and the address electrode A, so that predetermined wall charge is formed in the cell. A positive sustaining pulse is applied alternately to the display electrode Y and the display electrode X during the sustaining period. The display discharge is generated between the display electrodes (hereinafter referred to as XY-interelectrode) of the cell to be lighted by every application.
When the initialization period starts, i.e., when the sustaining period ends in the SF prior to the noted SF (hereinafter referred to as the previous SF), there are cells that have relatively much wall charge remained and cells that do not have. A lot of wall charge is remained in cells that were lighted correctly in the previous SF (hereinafter referred to as a “previous lighted cell”), while little wall charge is remained in cells that were kept in the non-lighted state correctly in the previous SF (hereinafter referred to as a “previous non-lighted cell”). Here, “correctly” means “in accordance with display data”. If the addressing process is performed in the state where charge quantity is different between cells, an error of generating address discharge in cells that are not to be lighted may occur easily. As a preparation process for improving reliability of the addressing process, the initialization process is important.
As explained above, the initialization in which the blunt wave is applied two times is effective for realizing the addressing process that is hardly affected by the influence of variation in the discharge characteristics between cells. The U.S. Pat. No. 5,745,086 discloses a method of decreasing the difference of wall voltages between the previous lighted cell and the previous non-lighted cell by applying the blunt wave the first time and equalizing the wall voltage of all cells to a predetermined value by applying the blunt wave the second time.
As being explained below, the initialization is performed so as to generate so-called microdischarge in the previous lighted cell as well as the previous non-lighted cell by each of the first application and the second application of the blunt wave in the conventional method.
FIGS. 4A and 4B show waveforms of voltage variation in the conventional initialization process. FIG. 4A corresponds to a part of the initialization period in FIG. 3. The potential of the display electrode Y increases from VY1′ to VY1 gently by the application of a positive blunt wave and then decreases from VY2′ to −VY2 gently by the application of a negative blunt wave. The word “gently” means that pulse discharge such as display discharge is not generated. At the start point of the application of the negative blunt wave, the offset bias to the display electrode X is switched from −VX1 to VX2.
For the consideration of discharge among three electrodes in a cell having a three-electrode structure, it is effective to pay attention to the XY-interelectrode and an AY-interelectrode (an interelectrode between an address electrode A and a display electrode Y). FIG. 4B shows variations of an applied voltage and a wall voltage at these two interelectrodes. The variation of the applied voltage is shown by a continuous line while the variation of the wall voltage is shown by a dotted line. However, it should be noted that the wall voltage is shown with positive and negative polarities inverted.
A state of a cell can be described by a cell voltage at the XY-interelectrode and a cell voltage at the AY-interelectrode. The cell voltage is a sum of the applied voltage and the wall voltage at each interelectrode. Since a polarity of the wall voltage is inverted in FIG. 4B, the distance between the dotted line and the continuous line indicates a value of the cell voltage at the corresponding interelectrode in the drawing. When the continuous line is above the dotted line, the cell voltage has the positive polarity. When the continuous line is below the dotted line, the cell voltage has the negative polarity.
In the discharge generated by the application of a blunt wave, a discharge start threshold level is an important parameter. Each electrode can be an anode or a cathode in the discharge at three interelectrodes, so there is a difference of discharge characteristics between the cases. Therefore, six discharge start threshold levels are defined as follows.
VtXY: a discharge start threshold level at the XY-interelectrode when the display electrode Y is a cathode
VtYX: a discharge start threshold level at the XY-interelectrode when the display electrode X is a cathode
VtAY: a discharge start threshold level at the AY-interelectrode when the display electrode Y is a cathode
VtYA: a discharge start threshold level at the AY-interelectrode when the address electrode A is a cathode
VtAX: a discharge start threshold level at the AX-interelectrode when the display electrode X is a cathode
VtXA: a discharge start threshold level at the AX-interelectrode when the address electrode A is a cathode
Here, the AX-interelectrode is an interelectrode between the address electrode A and the display electrode X.
FIG. 5 shows an example of a cell operation in the conventional initialization process. The wall voltage variation in the previous lighted cell is shown by a broken line, while the wall voltage variation in the previous non-lighted cell is shown by a dotted line. At the time tO just before the initialization, the wall voltage in the previous lighted cell has the negative polarity at the XY-interelectrode as well as at the AY-interelectrode (since the polarity is inverted, the dotted line and the broken line above the line that indicates zero volt correspond to negative wall voltages). On the other hand, the wall voltage in the previous non-lighted cell has the positive polarity at the XY-interelectrode as well as at the AY-interelectrode (note that the polarities are inverted).
When the first application of the blunt wave starts in the initialization process, the cell voltage increases. Since the previous lighted cell is charged more than the previous non-lighted cell, discharge at the XY-interelectrode starts in the previous lighted cell at the time t1 that is earlier than in the previous non-lighted cell. Once the discharge starts, electrification of the wall charge begins so as to keep the cell voltage at the discharge start threshold level VtYX, and a wall voltage is generated corresponding to the charge quantity (hereinafter, this phenomenon is expressed as “a wall voltage is written”). On this occasion, the wall voltage at the AY-interelectrode also changes simultaneously. However, the rate of the variation is smaller than that of the applied voltage to the AY-interelectrode, so the absolute value of the cell voltage at the AY-interelectrode increases. Discharge starts in the previous non-lighted cell at the time t2 when a certain period has passed after the start of the discharge in the previous lighted cell. Also in the previous non-lighted cell, a wall voltage is written so as to maintain the cell voltage at the discharge start threshold level VtYX.
In the example shown in FIG. 5, the cell voltage at the AY-interelectrode does not exceed the discharge start threshold level even after the application of the negative blunt wave is finished. Therefore, discharge that controls the cell voltage at the AY-interelectrode is not generated. A value of the wall voltage at the XY-interelectrode is VXY1−VtYX at the time t3 when the application of the negative blunt wave is finished. On the contrary, the wall voltage at the AY-interelectrode is not fixed.
Then the second application of the blunt wave starts. As the applied voltages at the XY-interelectrode and at the AY-interelectrode increase, the cell voltage also increases. The cell voltage at the XY-interelectrode exceeds the discharge start threshold level VtXY at the time t4. After the time t4, the wall voltage at the XY-interelectrode is written so as to keep the cell voltage at the XY-interelectrode at the discharge start threshold level VtXY. At the same time, the wall voltage at the AY-interelectrode is also written. However, since the wall voltage variation at the AY-interelectrode is smaller than that of the applied voltage, an absolute vale of the cell voltage at the AY-interelectrode increases.
In the example shown in FIG. 5, amplitude (a target voltage) of the blunt wave is small, and the cell voltage at the AY-interelectrode does not exceed the discharge start threshold level VtAY. A value of the wall voltage at the XY-interelectrode is a predetermined value VXY2−VtXY at the time t5 when the initialization process is finished. On the contrary, the wall voltage at the AY-interelectrode is not fixed.
The conventional driving method has a problem that an address discharge error can be generated when the wall voltage at the AY-interelectrode is not controlled in the initialization process. The wall voltage at the AY-interelectrode can be controlled in the same way as the wall voltage at the XY-interelectrode in the conventional driving method by increasing the applied voltage for the second application of the blunt wave. However, if the applied voltage is increased, discharge may start early in the previous non-lighted cell responding to the first application of the blunt wave. As a result, a light emission period of the previous non-lighted cell may be lengthened. Accordingly, background light emission may increase, and display contrast may be lowered. In addition, if the applied voltage is increased, requirement of a withstanding voltage for components of a driving circuit may become stricter resulting in a cost increase of the driving circuit. It is very difficult to determine a lower limit of write quantity of the wall voltage in the previous non-lighted cell while controlling complicated discharge in the three-electrode structure.